Process / pipelineDigital design automation
逻辑综合
逻辑综合是将高级硬件描述（Verilog/VHDL中的RTL）自动转换为优化后的门级网表的过程。逻辑综合由UC Berkeley的Brayton等人于20世纪80年代至90年代开创，它将行为规范转化为物理实现，并针对面积、速度和功耗进行优化。综合是现代数字设计的关键，它实现了最繁琐的手动任务的快速迭代和自动化。
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来源
- Brayton, R. K., Hachtel, G. D., McMullin, C. T., Sangiovanni-Vincentelli, A. L., & Vincentelli, A. S. (1987). Logic Synthesis for VLSI Design. Kluwer Academic. link ↗
- Mishchenko, A., Chatterjee, S., Brayton, R., & Sangiovanni-Vincentelli, A. L. (2006). DAG-aware AIG rewriting. In Proc. DAC (pp. 713-718). ACM. link ↗
- Berkeley, S. (1995). SIS: A system for sequential circuit synthesis. Technical Report UCB/ERL M95/55, UC Berkeley. link ↗
如何引用本页
ScholarGate. (2026, June 3). Logic Synthesis for Digital Circuit Design. ScholarGate. https://scholargate.app/zh/electrical-engineering/logic-synthesis
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