Process / pipelineDigital circuit verification
静态时序分析
静态时序分析（STA）是一种非仿真方法，用于验证数字电路是否满足时序约束（时钟频率、建立/保持时间、传播延迟）。STA由Bhatnagar等人于20世纪90年代系统性地提出，通过分析逻辑路径而不仿真向量来计算最坏情况和最佳情况的路径延迟。STA对于现代VLSI设计至关重要，它能够在芯片制造前快速实现时序收敛，并识别关键路径进行优化。
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来源
- Bhatnagar, H., & Bhatnagar, R. (1995). Static timing analysis: A primer. In VLSI Handbook (pp. 1-25). CRC Press. link ↗
- Shen, A., Ghosh, A., Madden, S. H., & Sorkin, F. (2003). Fast algorithms for static timing analysis. In Proc. ICCAD (pp. 126-131). IEEE. link ↗
- Berkelaar, M., Duffack, M., Flach, G., & Hartoog, R. (2007). OpenTimer: An open-source static timing analyzer. Proc. International Symposium on Circuits and Systems. link ↗
如何引用本页
ScholarGate. (2026, June 3). Static Timing Analysis for Digital Circuit Verification. ScholarGate. https://scholargate.app/zh/electrical-engineering/static-timing-analysis
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