方法证据记录
Logic Synthesis
Logic Synthesis is the automated conversion of high-level hardware descriptions (RTL in Verilog/VHDL) into optimized gate-level netlists. Pioneered by Brayton et al. at UC Berkeley in the 1980s-1990s, logic synthesis transforms behavioral specifications into physical implementations, optimizing for area, speed, and power. Synthesis is essential to modern digital design, enabling rapid iteration and automation of the most tedious manual tasks.
源记录
引文逐字复制自方法源记录。这些引文不代表任何层级的验证。
Logic Synthesis for Digital Circuit Design
分类方法记录 · process-pipeline / electrical-engineering
- Brayton, R. K., Hachtel, G. D., McMullin, C. T., Sangiovanni-Vincentelli, A. L., & Vincentelli, A. S. (1987). Logic Synthesis for VLSI Design. Kluwer Academic. · URL
- Mishchenko, A., Chatterjee, S., Brayton, R., & Sangiovanni-Vincentelli, A. L. (2006). DAG-aware AIG rewriting. In Proc. DAC (pp. 713-718). ACM. · URL
- Berkeley, S. (1995). SIS: A system for sequential circuit synthesis. Technical Report UCB/ERL M95/55, UC Berkeley. · URL
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