方法对比
并排查看您选择的方法；存在差异的行会高亮显示。
| 自动测试向量生成× | 静态时序分析× | |
|---|---|---|
| 领域 | 电气工程 | 电气工程 |
| 方法族 | Process / pipeline | Process / pipeline |
| 起源年份≠ | 1966 | 1995 |
| 提出者≠ | J. Paul Roth | Harish Bhatnagar |
| 类型≠ | Automated fault-detection test vector generation | Non-simulation timing verification for digital circuits |
| 开创性文献≠ | Abramovici, M., Breuer, M. A., & Friedman, A. D. (1990). Digital Systems Testing and Testable Design. Computer Science Press. link ↗ | Bhatnagar, H., & Bhatnagar, R. (1995). Static timing analysis: A primer. In VLSI Handbook (pp. 1-25). CRC Press. link ↗ |
| 别名 | ATPG, Test pattern generation, Fault-based testing | STA, Timing verification, Path-based timing |
| 相关 | 3 | 3 |
| 摘要≠ | Automatic Test Pattern Generation (ATPG) is the automated creation of test vectors that detect manufacturing defects in digital circuits. Pioneered by Roth in 1966, ATPG systematically finds inputs that make stuck-at faults observable at outputs, enabling comprehensive fault detection. ATPG is critical for semiconductor manufacturing: enabling high test coverage ensures only good chips ship and identifies manufacturing process issues. | Static Timing Analysis (STA) is a non-simulation method for verifying that digital circuits meet timing constraints (clock frequencies, setup/hold times, propagation delays). Introduced systematically by Bhatnagar et al. in the 1990s, STA computes worst-case and best-case path delays by analyzing logic paths without simulating vectors. STA is essential for modern VLSI design, enabling fast timing closure before silicon and identifying critical paths for optimization. |
| ScholarGate数据集 ↗ |
|
|