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	Syntéza logiky	Automatické generovanie testovacích vzoriek
Odbor	Elektrotechnika	Elektrotechnika
Rodina	Process / pipeline	Process / pipeline
Rok vzniku	1987	1966
Tvorca	Robert Brayton	J. Paul Roth
Typ	Automated conversion of HDL descriptions to gate-level netlists	Automated fault-detection test vector generation
Pôvodný zdroj	Brayton, R. K., Hachtel, G. D., McMullin, C. T., Sangiovanni-Vincentelli, A. L., & Vincentelli, A. S. (1987). Logic Synthesis for VLSI Design. Kluwer Academic.	Abramovici, M., Breuer, M. A., & Friedman, A. D. (1990). Digital Systems Testing and Testable Design. Computer Science Press.
Ďalšie názvy	RTL synthesis, Hardware synthesis, Logic optimization	ATPG, Test pattern generation, Fault-based testing
Príbuzné	3	3
Zhrnutie	Logic Synthesis is the automated conversion of high-level hardware descriptions (RTL in Verilog/VHDL) into optimized gate-level netlists. Pioneered by Brayton et al. at UC Berkeley in the 1980s-1990s, logic synthesis transforms behavioral specifications into physical implementations, optimizing for area, speed, and power. Synthesis is essential to modern digital design, enabling rapid iteration and automation of the most tedious manual tasks.	Automatic Test Pattern Generation (ATPG) is the automated creation of test vectors that detect manufacturing defects in digital circuits. Pioneered by Roth in 1966, ATPG systematically finds inputs that make stuck-at faults observable at outputs, enabling comprehensive fault detection. ATPG is critical for semiconductor manufacturing: enabling high test coverage ensures only good chips ship and identifies manufacturing process issues.