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	Automatické generovanie testovacích vzoriek	Statická časová analýza
Odbor	Elektrotechnika	Elektrotechnika
Rodina	Process / pipeline	Process / pipeline
Rok vzniku	1966	1995
Tvorca	J. Paul Roth	Harish Bhatnagar
Typ	Automated fault-detection test vector generation	Non-simulation timing verification for digital circuits
Pôvodný zdroj	Abramovici, M., Breuer, M. A., & Friedman, A. D. (1990). Digital Systems Testing and Testable Design. Computer Science Press.	Bhatnagar, H., & Bhatnagar, R. (1995). Static timing analysis: A primer. In VLSI Handbook (pp. 1-25). CRC Press.
Ďalšie názvy	ATPG, Test pattern generation, Fault-based testing	STA, Timing verification, Path-based timing
Príbuzné	3	3
Zhrnutie	Automatic Test Pattern Generation (ATPG) is the automated creation of test vectors that detect manufacturing defects in digital circuits. Pioneered by Roth in 1966, ATPG systematically finds inputs that make stuck-at faults observable at outputs, enabling comprehensive fault detection. ATPG is critical for semiconductor manufacturing: enabling high test coverage ensures only good chips ship and identifies manufacturing process issues.	Static Timing Analysis (STA) is a non-simulation method for verifying that digital circuits meet timing constraints (clock frequencies, setup/hold times, propagation delays). Introduced systematically by Bhatnagar et al. in the 1990s, STA computes worst-case and best-case path delays by analyzing logic paths without simulating vectors. STA is essential for modern VLSI design, enabling fast timing closure before silicon and identifying critical paths for optimization.