Shared Memory and Consistency

Shared-memory architecture lets multiple processors operate on a common address space; a memory consistency model defines the order in which one processor's memory operations become visible to others, the contract parallel programs rely on.

Definition

A memory consistency model is the specification of the allowable orderings of memory reads and writes across processors in a shared-memory system, defining what values a load may return and thereby the contract between hardware and concurrent software.

Scope

This topic covers shared-memory multiprocessing and, centrally, memory consistency models: sequential consistency, relaxed and weak models, memory fences, and the relationship between consistency and coherence. It also covers synchronization primitives that rely on the consistency model. It excludes the per-location coherence mechanism (cache coherence protocols) and the chip-level integration of cores (multicore and chip multiprocessors).

Core questions

• What ordering of memory operations may parallel programs assume?
• How does sequential consistency differ from relaxed consistency models?
• Why do relaxed models exist, and how do memory fences restore needed ordering?
• How do coherence and consistency together define correct shared-memory behavior?

Key concepts

• shared address space
• memory consistency model
• sequential consistency
• relaxed and weak consistency
• memory fences and barriers
• consistency vs coherence
• synchronization primitives
• data races

Key theories

Sequential consistency

Lamport's sequential consistency requires that the result of execution be as if all processors' operations were interleaved in some single global order that respects each processor's program order; it is intuitive but constrains hardware optimization, motivating relaxed models.

Mechanisms

Hardware reorders and buffers memory operations for performance, so the consistency model specifies which reorderings are visible to other processors. Sequential consistency forbids visible reordering across processors; relaxed models permit certain reorderings for speed and require programmers to insert memory fences to enforce ordering where needed. Synchronization primitives such as locks and atomic operations are built on these guarantees, and programs that avoid data races behave predictably.

Clinical relevance

The memory consistency model is the foundation of correct concurrent programming: it determines what a multithreaded program may legitimately assume about the visibility and ordering of shared updates. Misunderstanding it causes subtle, hard-to-reproduce bugs, and language memory models (as in C++ and Java) build directly on these hardware concepts.

History

Lamport formalized sequential consistency in 1979. As hardware grew more aggressive in reordering memory accesses for performance, relaxed consistency models proliferated across architectures in the 1980s and 1990s, prompting work to define and tame them and, eventually, to give programming languages their own well-specified memory models.

Debates

Strong versus relaxed consistency

Strong models like sequential consistency are easier to reason about but limit hardware performance, while relaxed models enable optimization at the cost of programmer complexity; the field continues to balance intuitive semantics against efficiency through carefully specified models and fences.

Key figures

• Leslie Lamport
• Sarita Adve
• Mark D. Hill
• David E. Culler

Seminal works

• hennessy2019
• culler1999

Frequently asked questions

What is the difference between coherence and consistency?

Coherence guarantees that all processors eventually agree on the value of each individual memory location and see writes to it in a sensible order. Consistency governs the ordering of operations across different locations as observed by different processors. A consistency model presupposes coherence and adds cross-location ordering rules.

Why do processors use relaxed memory models?

Strict ordering would force the hardware to forgo buffering and reordering that hide memory latency, hurting performance. Relaxed models let the hardware optimize freely and give programmers explicit fences to enforce ordering only where correctness requires it.