Static Timing Analysis
Static Timing Analysis (STA) is a non-simulation method for verifying that digital circuits meet timing constraints (clock frequencies, setup/hold times, propagation delays). Introduced systematically by Bhatnagar et al. in the 1990s, STA computes worst-case and best-case path delays by analyzing logic paths without simulating vectors. STA is essential for modern VLSI design, enabling fast timing closure before silicon and identifying critical paths for optimization.
Izvorni zapis
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- Bhatnagar, H., & Bhatnagar, R. (1995). Static timing analysis: A primer. In VLSI Handbook (pp. 1-25). CRC Press. · URL
- Shen, A., Ghosh, A., Madden, S. H., & Sorkin, F. (2003). Fast algorithms for static timing analysis. In Proc. ICCAD (pp. 126-131). IEEE. · URL
- Berkelaar, M., Duffack, M., Flach, G., & Hartoog, R. (2007). OpenTimer: An open-source static timing analyzer. Proc. International Symposium on Circuits and Systems. · URL
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