Why does DRAM need to be refreshed but SRAM does not?

DRAM stores each bit as charge on a capacitor, which slowly leaks away, so the contents must be periodically read and rewritten (refreshed) to avoid loss. SRAM holds each bit in a latch that retains its state as long as power is supplied, so it needs no refresh.

Why is SRAM used for caches and DRAM for main memory?

SRAM is much faster but larger per bit and more expensive, making it ideal for small, speed-critical caches. DRAM is denser and cheaper per bit but slower, making it suitable for the large main memory where capacity matters more than raw latency.

Memory Technologies and DRAM

Memory technologies are the physical devices that store data at the main-memory level — chiefly dynamic RAM (DRAM) for capacity and static RAM (SRAM) for speed — whose timing, bandwidth, and organization set the performance floor of the memory hierarchy.

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Definition

Memory technologies are the semiconductor and related devices used to implement computer memory, most importantly DRAM, which stores each bit as charge on a capacitor and must be periodically refreshed, and SRAM, which stores bits in latches for faster but less dense storage.

Scope

This topic covers the device technologies behind memory: SRAM cells used in caches, DRAM cells and their need for refresh, DRAM organization into banks, rows, and columns, the timing parameters and standards (such as the DDR families), memory bandwidth and channels, and emerging non-volatile memories. It excludes cache and OS-level management of memory (cache organization and policies, virtual memory and paging) and persistent secondary storage devices (secondary storage devices).

Core questions

How do SRAM and DRAM cells differ in speed, density, cost, and power?
Why must DRAM be refreshed, and how is it organized into banks, rows, and columns?
What timing parameters and standards govern DRAM access and bandwidth?
How do emerging non-volatile memories fit into the memory hierarchy?

Key concepts

SRAM cell
DRAM cell and refresh
banks, rows, and columns
row activation and precharge
DDR memory standards
memory bandwidth and channels
memory latency
non-volatile memory

Mechanisms

An SRAM cell holds a bit in a small latch, giving fast access but low density. A DRAM cell stores a bit as charge on a tiny capacitor, which leaks and must be refreshed periodically. DRAM chips are organized into banks of rows and columns; an access activates a row into a sense-amplifier buffer, then reads or writes columns from it. Double-data-rate (DDR) interfaces and multiple channels raise bandwidth, while latency is set by row-activation and column-access timings.

Clinical relevance

Because processors greatly outpace memory, DRAM characteristics — latency, bandwidth, and the cost of row activation — directly shape system performance and motivate the entire cache hierarchy. The properties of DRAM also create reliability and security concerns, such as the Rowhammer disturbance effect, and emerging non-volatile memories are reshaping how systems combine memory and storage.

History

Robert Dennard invented the one-transistor DRAM cell at IBM in 1966–1968, and DRAM became the dominant main-memory technology. Successive synchronous and double-data-rate (DDR) standards raised bandwidth over decades, while SRAM remained the technology of on-chip caches. Non-volatile and stacked memories later emerged to address capacity and the persistent-memory frontier.

Key figures

Robert Dennard
John L. Hennessy
David A. Patterson
Bruce Jacob

Seminal works

hennessy2019
jacob2008

Frequently asked questions

Why does DRAM need to be refreshed but SRAM does not?: DRAM stores each bit as charge on a capacitor, which slowly leaks away, so the contents must be periodically read and rewritten (refreshed) to avoid loss. SRAM holds each bit in a latch that retains its state as long as power is supplied, so it needs no refresh.
Why is SRAM used for caches and DRAM for main memory?: SRAM is much faster but larger per bit and more expensive, making it ideal for small, speed-critical caches. DRAM is denser and cheaper per bit but slower, making it suitable for the large main memory where capacity matters more than raw latency.