ScholarGate
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Process / pipelineControl systems, signal processing

锁相环

锁相环（PLL）是一种反馈控制系统，用于将输出振荡器同步到输入信号的相位和频率。PLL由Gardner于1966年提出，在通信、雷达、时钟分配和电力系统中无处不在。PLL持续调整其振荡器频率以最小化与输入的相位误差，从而实现锁定。PLL是现代电子系统的基础。

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锁相环
下垂控制S参数分析传输线矩阵法

来源

  1. Gardner, F. M. (1966). Phaselock Techniques. Wiley & Sons. link ↗
  2. Wolaver, D. H. (1991). Phase-Locked-Loop Circuit Design. Prentice Hall. link ↗
  3. Best, R. E. (2007). Phase-Locked Loops: Design, Simulation, and Applications (5th ed.). McGraw-Hill. link ↗

如何引用本页

ScholarGate. (2026, June 3). Phase-Locked Loop for Frequency Synchronization and Clock Recovery. ScholarGate. https://scholargate.app/zh/electrical-engineering/phase-locked-loop

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下垂控制

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ScholarGate — Phase-Locked Loop (Phase-Locked Loop for Frequency Synchronization and Clock Recovery). 于 2026-06-15 检索自 https://scholargate.app/zh/electrical-engineering/phase-locked-loop · 数据集： https://doi.org/10.5281/zenodo.20539026