เปรียบเทียบวิธี

	การวิเคราะห์เวลาแบบสถิต	การสร้างชุดทดสอบอัตโนมัติ
สาขาวิชา	วิศวกรรมไฟฟ้า	วิศวกรรมไฟฟ้า
ตระกูล	Process / pipeline	Process / pipeline
ปีกำเนิด	1995	1966
ผู้ริเริ่ม	Harish Bhatnagar	J. Paul Roth
ประเภท	Non-simulation timing verification for digital circuits	Automated fault-detection test vector generation
แหล่งต้นตำรับ	Bhatnagar, H., & Bhatnagar, R. (1995). Static timing analysis: A primer. In VLSI Handbook (pp. 1-25). CRC Press.	Abramovici, M., Breuer, M. A., & Friedman, A. D. (1990). Digital Systems Testing and Testable Design. Computer Science Press.
ชื่อเรียกอื่น	STA, Timing verification, Path-based timing	ATPG, Test pattern generation, Fault-based testing
ที่เกี่ยวข้อง	3	3
สรุป	Static Timing Analysis (STA) is a non-simulation method for verifying that digital circuits meet timing constraints (clock frequencies, setup/hold times, propagation delays). Introduced systematically by Bhatnagar et al. in the 1990s, STA computes worst-case and best-case path delays by analyzing logic paths without simulating vectors. STA is essential for modern VLSI design, enabling fast timing closure before silicon and identifying critical paths for optimization.	Automatic Test Pattern Generation (ATPG) is the automated creation of test vectors that detect manufacturing defects in digital circuits. Pioneered by Roth in 1966, ATPG systematically finds inputs that make stuck-at faults observable at outputs, enabling comprehensive fault detection. ATPG is critical for semiconductor manufacturing: enabling high test coverage ensures only good chips ship and identifies manufacturing process issues.