I/O Architecture and Buses

I/O architecture defines how a processor and memory communicate with peripheral devices through buses, controllers, interrupts, and addressing schemes, governing how commands and data flow to and from the outside world.

Definition

I/O architecture and buses are the organization and interconnects by which a computer's processor and memory exchange control signals and data with peripheral devices, including the addressing of device registers and the mechanisms by which devices request service.

Scope

This topic covers the structure of input/output: buses and point-to-point interconnects, device controllers and registers, memory-mapped versus port-mapped I/O, polling and interrupt-driven I/O, and bus protocols and arbitration. It treats how devices are connected and controlled. It excludes the bulk-transfer DMA mechanism and virtualization (I/O virtualization and DMA) and the storage media themselves (secondary storage devices).

Core questions

• How are peripheral devices addressed and controlled by the processor?
• How do memory-mapped and port-mapped I/O differ?
• How do polling and interrupt-driven I/O compare in efficiency?
• How do buses and point-to-point interconnects arbitrate and transfer data?

Key concepts

• device controllers and registers
• memory-mapped I/O
• port-mapped I/O
• polling
• interrupts and interrupt handlers
• buses and interconnects
• bus arbitration
• I/O addressing

Key theories

Interrupt-driven I/O

Rather than continuously polling a device, the processor proceeds with other work and is notified by an interrupt when the device needs attention, greatly improving efficiency for devices that are slow or operate intermittently.

Mechanisms

Each device is managed by a controller exposing registers that the processor reads and writes, either through memory-mapped addresses or special I/O ports. The processor can poll these registers or, more efficiently, enable interrupts so the device signals when ready. Buses connect components and arbitrate access among multiple masters, while modern systems increasingly use high-speed point-to-point serial links instead of shared parallel buses.

Clinical relevance

I/O architecture determines how efficiently a system communicates with storage, network, and other devices. Interrupt-driven I/O frees the processor for useful work, and the evolution from shared buses to fast serial interconnects such as PCI Express underpins the bandwidth needed by modern storage, networking, and accelerator hardware.

History

Early systems used programmed I/O and shared parallel buses with central arbitration. Interrupt mechanisms and standardized buses such as ISA and PCI improved flexibility and performance. The shift to high-speed point-to-point serial interconnects, exemplified by PCI Express, addressed the bandwidth and signaling limits of shared parallel buses.

Key figures

• John L. Hennessy
• David A. Patterson
• Abraham Silberschatz

Seminal works

• hennessy2019
• silberschatz2018

Frequently asked questions

What is the difference between memory-mapped and port-mapped I/O?

Memory-mapped I/O assigns device registers addresses within the regular memory address space, so ordinary load and store instructions access them. Port-mapped I/O uses a separate address space and special instructions for device access. Memory-mapped I/O is more common in modern architectures.

Why are interrupts better than polling for most devices?

Polling wastes processor cycles repeatedly checking whether a device is ready. Interrupts let the processor do other work and be notified only when the device actually needs service, which is far more efficient for devices that are slow or respond unpredictably.