ScholarGate
Asistent
Process / pipelineControl systems, signal processing

Faza-vezana petlja

Faza-vezana petlja (PLL) je sustav povratne sprege koji sinkronizira izlazni oscilator kako bi odgovarao fazi i frekvenciji ulaznog signala. Uvedene od strane Gardnera 1966., PLL-ovi su sveprisutni u komunikacijama, radaru, distribuciji takta i energetskim sustavima. PLL kontinuirano prilagođava frekvenciju svog oscilatora kako bi minimizirao faznu pogrešku s ulazom, postižući zaključavanje. PLL-ovi su temeljni za moderne elektroničke sustave.

Otvorite u MethodMindUskoroVideoUskoroDownload slides

Pročitajte cijelu metodu

Samo za članove

Prijavite se besplatnim računom kako biste pročitali ovaj odjeljak.

Prijavite se

Method map

The neighbourhood of related methods — select a node to explore.

Izvori

  1. Gardner, F. M. (1966). Phaselock Techniques. Wiley & Sons. link
  2. Wolaver, D. H. (1991). Phase-Locked-Loop Circuit Design. Prentice Hall. link
  3. Best, R. E. (2007). Phase-Locked Loops: Design, Simulation, and Applications (5th ed.). McGraw-Hill. link

Kako citirati ovu stranicu

ScholarGate. (2026, June 3). Phase-Locked Loop for Frequency Synchronization and Clock Recovery. ScholarGate. https://scholargate.app/hr/electrical-engineering/phase-locked-loop

Which method?

Set this method beside its closest kin and read them side by side — the library lays the books on the table; the choice is yours.

Compare side by side

Citirana u

ScholarGatePhase-Locked Loop (Phase-Locked Loop for Frequency Synchronization and Clock Recovery). Preuzeto 2026-06-15 s https://scholargate.app/hr/electrical-engineering/phase-locked-loop · Skup podataka: https://doi.org/10.5281/zenodo.20539026