Comparar métodos
Revisa los métodos seleccionados uno junto a otro; las filas que difieren aparecen resaltadas.
| Generación Automática de Patrones de Prueba× | Síntesis Lógica× | |
|---|---|---|
| Campo | Ingeniería eléctrica | Ingeniería eléctrica |
| Familia | Process / pipeline | Process / pipeline |
| Año de origen≠ | 1966 | 1987 |
| Autor original≠ | J. Paul Roth | Robert Brayton |
| Tipo≠ | Automated fault-detection test vector generation | Automated conversion of HDL descriptions to gate-level netlists |
| Fuente seminal≠ | Abramovici, M., Breuer, M. A., & Friedman, A. D. (1990). Digital Systems Testing and Testable Design. Computer Science Press. link ↗ | Brayton, R. K., Hachtel, G. D., McMullin, C. T., Sangiovanni-Vincentelli, A. L., & Vincentelli, A. S. (1987). Logic Synthesis for VLSI Design. Kluwer Academic. link ↗ |
| Alias | ATPG, Test pattern generation, Fault-based testing | RTL synthesis, Hardware synthesis, Logic optimization |
| Relacionados | 3 | 3 |
| Resumen≠ | Automatic Test Pattern Generation (ATPG) is the automated creation of test vectors that detect manufacturing defects in digital circuits. Pioneered by Roth in 1966, ATPG systematically finds inputs that make stuck-at faults observable at outputs, enabling comprehensive fault detection. ATPG is critical for semiconductor manufacturing: enabling high test coverage ensures only good chips ship and identifies manufacturing process issues. | Logic Synthesis is the automated conversion of high-level hardware descriptions (RTL in Verilog/VHDL) into optimized gate-level netlists. Pioneered by Brayton et al. at UC Berkeley in the 1980s-1990s, logic synthesis transforms behavioral specifications into physical implementations, optimizing for area, speed, and power. Synthesis is essential to modern digital design, enabling rapid iteration and automation of the most tedious manual tasks. |
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