Compara mètodes

	Anàlisi Estàtica de Temps	Generació Automàtica de Patrons de Prova
Camp	Enginyeria elèctrica	Enginyeria elèctrica
Família	Process / pipeline	Process / pipeline
Any d'origen	1995	1966
Autor original	Harish Bhatnagar	J. Paul Roth
Tipus	Non-simulation timing verification for digital circuits	Automated fault-detection test vector generation
Font seminal	Bhatnagar, H., & Bhatnagar, R. (1995). Static timing analysis: A primer. In VLSI Handbook (pp. 1-25). CRC Press.	Abramovici, M., Breuer, M. A., & Friedman, A. D. (1990). Digital Systems Testing and Testable Design. Computer Science Press.
Àlies	STA, Timing verification, Path-based timing	ATPG, Test pattern generation, Fault-based testing
Relacionats	3	3
Resum	Static Timing Analysis (STA) is a non-simulation method for verifying that digital circuits meet timing constraints (clock frequencies, setup/hold times, propagation delays). Introduced systematically by Bhatnagar et al. in the 1990s, STA computes worst-case and best-case path delays by analyzing logic paths without simulating vectors. STA is essential for modern VLSI design, enabling fast timing closure before silicon and identifying critical paths for optimization.	Automatic Test Pattern Generation (ATPG) is the automated creation of test vectors that detect manufacturing defects in digital circuits. Pioneered by Roth in 1966, ATPG systematically finds inputs that make stuck-at faults observable at outputs, enabling comprehensive fault detection. ATPG is critical for semiconductor manufacturing: enabling high test coverage ensures only good chips ship and identifies manufacturing process issues.