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| Tạo Mẫu Kiểm Thử Tự Động× | Phân tích thời gian tĩnh× | |
|---|---|---|
| Lĩnh vực | Kỹ thuật điện | Kỹ thuật điện |
| Họ | Process / pipeline | Process / pipeline |
| Năm ra đời≠ | 1966 | 1995 |
| Người khởi xướng≠ | J. Paul Roth | Harish Bhatnagar |
| Loại≠ | Automated fault-detection test vector generation | Non-simulation timing verification for digital circuits |
| Công trình gốc≠ | Abramovici, M., Breuer, M. A., & Friedman, A. D. (1990). Digital Systems Testing and Testable Design. Computer Science Press. link ↗ | Bhatnagar, H., & Bhatnagar, R. (1995). Static timing analysis: A primer. In VLSI Handbook (pp. 1-25). CRC Press. link ↗ |
| Tên gọi khác | ATPG, Test pattern generation, Fault-based testing | STA, Timing verification, Path-based timing |
| Liên quan | 3 | 3 |
| Tóm tắt≠ | Automatic Test Pattern Generation (ATPG) is the automated creation of test vectors that detect manufacturing defects in digital circuits. Pioneered by Roth in 1966, ATPG systematically finds inputs that make stuck-at faults observable at outputs, enabling comprehensive fault detection. ATPG is critical for semiconductor manufacturing: enabling high test coverage ensures only good chips ship and identifies manufacturing process issues. | Static Timing Analysis (STA) is a non-simulation method for verifying that digital circuits meet timing constraints (clock frequencies, setup/hold times, propagation delays). Introduced systematically by Bhatnagar et al. in the 1990s, STA computes worst-case and best-case path delays by analyzing logic paths without simulating vectors. STA is essential for modern VLSI design, enabling fast timing closure before silicon and identifying critical paths for optimization. |
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