Pipelining and Hazards
Pipelining overlaps the execution of consecutive instructions by dividing instruction processing into stages, increasing throughput; hazards are the situations — resource conflicts, data dependencies, and branches — that prevent the next instruction from proceeding in the following cycle.
Definition
Pipelining is a technique that overlaps the execution of multiple instructions by partitioning their processing into sequential stages, and a hazard is any condition that forces a stage to stall because it cannot correctly proceed in the next clock cycle.
Scope
This topic covers the classic instruction pipeline and the three hazard classes that limit it: structural hazards (resource conflicts), data hazards (dependencies between instructions), and control hazards (branches). It includes the standard remedies — forwarding/bypassing, stalling, and branch handling. It excludes advanced parallel issue (instruction-level parallelism), branch-direction prediction in depth (branch prediction), and dynamic reordering (out-of-order execution).
Core questions
- How does dividing instruction execution into stages increase throughput without reducing latency?
- What are structural, data, and control hazards, and what causes each?
- How does forwarding resolve many data hazards without stalling?
- What is the cost of branches in a pipeline, and how is it mitigated?
Key concepts
- pipeline stages (fetch, decode, execute, memory, writeback)
- throughput vs latency
- structural hazards
- data hazards
- control hazards
- forwarding and bypassing
- pipeline stalls and bubbles
- branch penalty
Key theories
- Pipeline throughput and hazards
- A k-stage pipeline ideally completes one instruction per cycle after fill, but structural, data, and control hazards introduce stalls that reduce throughput below the ideal; pipeline design centers on minimizing these stalls.
Mechanisms
Instruction processing is split into stages so that while one instruction is executing, others are being fetched and decoded. A structural hazard arises when two instructions need the same resource; a data hazard when an instruction needs a result not yet produced; a control hazard when the next instruction depends on an unresolved branch. Forwarding routes results directly between stages, stalls insert bubbles when forwarding is insufficient, and branch handling reduces control-hazard penalties.
Clinical relevance
Pipelining is the foundational performance technique in virtually every processor, and understanding hazards explains why instruction ordering and branch behavior affect speed. Compiler instruction scheduling and programmer awareness of dependencies and branch patterns can materially improve performance on pipelined hardware.
History
Pipelining appeared in early high-performance machines such as the IBM Stretch and CDC 6600 in the early 1960s. The simple five-stage pipeline became a canonical teaching and design model with the RISC processors of the 1980s, and the systematic classification of hazards and their remedies was codified in the Hennessy-Patterson texts.
Key figures
- John L. Hennessy
- David A. Patterson
- Seymour Cray
Related topics
Seminal works
- hennessy2019
- patterson2020
Frequently asked questions
- Does pipelining make a single instruction run faster?
- No. Pipelining does not reduce the time to complete one instruction (latency); it increases how many instructions finish per unit time (throughput) by overlapping their execution, much as an assembly line raises output without speeding up any single item.
- What is forwarding?
- Forwarding, or bypassing, routes a freshly computed result directly from the stage that produced it to a later stage that needs it, instead of waiting for it to be written back to the register file. This resolves many data hazards without stalling the pipeline.