Automatic Test Pattern Generation
Also known as: ATPG, Test pattern generation, Fault-based testing
Automatic Test Pattern Generation (ATPG) is the automated creation of test vectors that detect manufacturing defects in digital circuits. Pioneered by Roth in 1966, ATPG systematically finds inputs that make stuck-at faults observable at outputs, enabling comprehensive fault detection. ATPG is critical for semiconductor manufacturing: enabling high test coverage ensures only good chips ship and identifies manufacturing process issues.
Key highlights
- Systematic fault-driven approach: targets specific defects rather than random testing
- High fault coverage: modern ATPG achieves >95% stuck-at fault coverage on well-designed circuits
- Automated process: no manual test vector creation needed
- Identifies untestable faults: reveals design-for-testability (DFT) gaps
Intuition
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How it works
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When to use it
ATPG is mandatory for any digital IC shipped to customers. Used in manufacturing test: every chip undergoes ATPG-generated tests before shipment. Essential for cost control: detecting defects early avoids expensive field failures. Run alongside design synthesis to identify hard-to-test logic (use DFT to improve testability). Less critical for safety-non-critical products, but standard industry practice.
Strengths & limitations
- Systematic fault-driven approach: targets specific defects rather than random testing
- High fault coverage: modern ATPG achieves >95% stuck-at fault coverage on well-designed circuits
- Automated process: no manual test vector creation needed
- Identifies untestable faults: reveals design-for-testability (DFT) gaps
- Exponential complexity: some faults require exponential search to find tests (NP-complete problem)
- Limited to assumed fault models (stuck-at); may miss real defects not matching the model
- Difficulty with sequential circuits: test generation requires long test sequences
- Untestable faults exist in any design: some faults cannot be detected without modifying the circuit
Common pitfalls
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Applications
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Frequently asked
What is a stuck-at fault and why is it the standard fault model?
A stuck-at fault assumes a line is permanently 0 or 1 (stuck-at-0 or stuck-at-1) due to defects. It's standard because it's simple to model and covers many real manufacturing defects (opens, shorts). More complex models (bridging, transition) exist but are harder to test.
Why do some faults remain untestable?
Untestable faults occur when: (1) the fault site is not observable at any output, or (2) the fault cannot be activated without violating other constraints. Design-for-testability (scan chains) adds observability; BIST adds self-checking.
How do I improve test coverage if ATPG reports low coverage?
Add design-for-testability (DFT): scan chains for sequential logic, test points for hard-to-access nodes, and BIST for self-checking. These modifications improve observability and controllability, raising coverage.
What is the relationship between test time and test cost?
Longer tests improve fault coverage but increase per-chip test time and equipment cost. Balance coverage and time via compression: multiple faults per test vector, test vector compression, and parallel testing.
Sources
- 1.Abramovici, M., Breuer, M. A., & Friedman, A. D. (1990). Digital Systems Testing and Testable Design. Computer Science Press.
- 2.Roth, J. P. (1966). Diagnosis of automata failures: A calculus and a method. IBM Journal of Research and Development, 10(4), 278-291.
- 3.Goel, P. (1981). An implicit enumeration algorithm to generate tests for combinational circuits. IEEE Transactions on Computers, 30(3), 215-222.
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Cite this page
ScholarGate. (2026, June 3). Automatic Test Pattern Generation. ScholarGate. https://scholargate.app/electrical-engineering/automatic-test-pattern-generation